Datasheet

Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 540 of 788
REJ09B0300-0300
R/W
Bit Bit Name Initial Value Slave Host Description
1 LSMIB 0 R/W — LSMI Output Bit
Controls LSMI output in combination with the LSMIE
bit. For details, refer to description on the LSMIE bit
in HICR0.
0 LSCIB 0 R/W — LSCI output Bit
Controls LSCI output in combination with the LSCIE
bit. For details, refer to description on the LSCIE bit
in HICR0.
19.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3)
Bits 6 to 0 in HICR2 control interrupts from the host interface (LPC) module to the slave
processor (this LSI). Bit 7 in HICR2 and HICR3 monitor host interface pin states.
The pin states can be monitored regardless of the host interface operating state or the operating
state of the functions that use pin multiplexing.
• HICR2
R/W
Bit Bit Name Initial Value Slave Host Description
7 GA20 Undefined R — GA20 Pin Monitor
6 LRST 0 R/(W)
*
— LPC Reset Interrupt Flag
This bit is a flag that generates an ERRI interrupt
when an LPC hardware reset occurs.
0: [Clearing condition]
Writing 0 after reading LRST = 1
1: [Setting condition]
LRESET pin falling edge detection