Datasheet

Section 1 Overview
Rev. 3.00 Mar 21, 2006 page 3 of 788
REJ09B0300-0300
1.2 Block Diagram
H8S/2000 CPU
DTC
Interrup
controller
WDT× 2 channels
ROM
(Flash memory)
RAM
8-bit PWM
16-bit FRT
8-bit timer × 4 channels
Timer connection
14-bit PWM
Host interfaces
(LPC
*
, XBS)
10-bit A/D converter
8-bit D/A converter
SCI × 3 channels
(IrDA × 1 channel)
IIC × 2 channels
P17/A7/PW7
P16/A6/PW6
P15/A5/PW5
P14/A4/PW4
P13/A3/PW3
P12/A2/PW2
P11/A1/PW1
P10/A0/PW0
P27/A15/PW15/CBLANK
P26/A14/PW14
P25/A13/PW13
P24/A12/PW12
P23/A11/PW11
P22/A10/PW10
P21/A9/PW9
P20/A8/PW8
PA7/A23/KIN15/CIN15/PS2CD
PA6/A22/KIN14/CIN14/PS2CC
PA5/A21/KIN13/CIN13/PS2BD
PA4/A20/KIN12/CIN12/PS2BC
PA3/A19/KIN11/CIN11/PS2AD
PA2/A18/KIN10/CIN10/PS2AC
PA1/A17/KIN9/CIN9
PA0/A16/KIN8/CIN8
P37/D15/HDB7/SERIRQ*
P36/D14/HDB6/LCLK*
P35/D13/HDB5/LRESET*
P34/D12/HDB4/LFRAME*
P33/D11/HDB3/LAD3*
P32/D10/HDB2/LAD2*
P31/D9/HDB1/LAD1*
P30/D8/HDB0/LAD0*
PB7/D7/WUE7*
PB6/D6/WUE6*
PB5/D5/WUE5*
PB4/D4/WUE4*
PB3/D3/WUE3*/CS4
PB2/D2/WUE2*/CS3
PB1/D1/WUE1*/HIRQ4/LSCI*
PB0/D0/WUE0*/HIRQ3/LSMI*
P97/WAIT/SDA0
P96/φ/EXCL
P95/AS/IOS/CS1
P94/HWR/IOW
P93/RD/IOR
P92/IRQ0
P91/IRQ1
P90/LWR/IRQ2/ADTRG/ECS2
P67/TMOX/CIN7/KIN7/IRQ7
P66/FTOB/CIN6/KIN6/IRQ6
P65/FTID/CIN5/KIN5
P64/FTIC/CIN4/KIN4/CLAMPO
P63/FTIB/CIN3/KIN3/VFBACKI
P62/FTIA/CIN2/KIN2/VSYNCI/TMIY
P61/FTOA/CIN1/KIN1/VSYNCO
P60/FTCI/CIN0/KIN0/HFBACKI/TMIX
P47/PWX1
P46/PWX0
P45/TMRI1/HIRQ12/CSYNCI
P44/TMO1/HIRQ1/HSYNCO
P43/TMCI1/HIRQ11/HSYNCI
P42/TMRI0/SCK2/SDA1
P41/TMO0/RxD2/IrRxD
P40/TMCI0/TxD2/IrTxD
P52/SCK0/SCL0
P51/RxD0
P50/TxD0
P77/AN7/DA1 P76/AN6/DA0 P75/AN5 P74/AN4 P73/AN3 P72/AN2 P71/AN1 P70/AN0
P86/IRQ5/SCK1/SCL1 P85/IRQ4/RxD1 P84/IRQ3/TxD1 P83/LPCPD* P82/HIFSD/CLKRUN* P81/CS2/GA20 P80/HA0/PME*
AVref AVCC AVSS
RES
XTAL
EXTAL
VCCB
MD1
MD0
NMI
STBY
RESO
VCC VCL VSS VSS VSS VSS
Port 8
Port 7
Clock pulse generator
Internal data bus
Internal address bus
Bus controller
Port APort 2Port 1Port 3Port B
Port 9Port 6Port 4Port 5
Note: * The LPC function and the WUE pin function are not supported by the H8S/2148B and H8S/2145B (5-version).
Keyboard buffer
controller × 3 channels
Figure 1.1 Internal Block Diagram of H8S/2140B, H8S/2141B, H8S/2145B, and H8S/2148B