Datasheet

Section 19 Host Interface LPC Interface (LPC)
Rev. 3.00 Mar 21, 2006 page 532 of 788
REJ09B0300-0300
19.3 Register Descriptions
The LPC has the following registers. The settings of XBS related bits do not affect the operation
of this LSI’s LPC. However, for reasons relating to the configuration of the program development
tool (emulator), when the LPC is used, bit HI12E in SYSCR2 should not be set to 1. For details,
see section 3.2.2, System Control Register (SYSCR), and section 18.3.1, System Control Register
2 (SYSCR2).
• Host interface control register 0 (HICR0)
• Host interface control register 1 (HICR1)
• Host interface control register 2 (HICR2)
• Host interface control register 3 (HICR3)
• LPC channel 3 address registers (LADR3H, LADR3L)
• Input data register 1 (IDR1)
• Output data register 1 (ODR1)
• Status register 1 (STR1)
• Input data register 2 (IDR2)
• Output data register 2 (ODR2)
• Status register 2 (STR2)
• Input data register 3 (IDR3)
• Output data register 3 (ODR3)
• Status register 3 (STR3)
• Bidirectional data registers 0 to 15 (TWR0 to TWR15)
• SERIRQ control register 0 (SIRQCR0)
• SERIRQ control register 1 (SIRQCR1)
• Host interface select register (HISEL)