Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 526 of 788
REJ09B0300-0300
Table 18.9 HIRQ Setting/Clearing Conditions
Host Interrupt
Signal
Setting Condition Clearing Condition
HIRQ11
(P43)
Internal CPU reads 0 from bit P43DR, then
writes 1
Internal CPU writes 0 in bit P43DR, or
host reads output data register_2
(ODR_2)
HIRQ1
(P44)
Internal CPU reads 0 from bit P44DR, then
writes 1
Internal CPU writes 0 in bit P44DR, or
host reads output data register_1
(ODR_1)
HIRQ12
(P45)
Internal CPU reads 0 from bit P45DR, then
writes 1
Internal CPU writes 0 in bit P45DR, or
host reads output data register_1
(ODR_1)
HIRQ3
(PB0)
Internal CPU reads 0 from bit PB0ODR,
then writes 1
Internal CPU writes 0 in bit PB0ODR,
or host reads output data register_3
(ODR_3)
HIRQ4
(PB1)
Internal CPU reads 0 from bit PB1ODR,
then writes 1
Internal CPU writes 0 in bit PB1ODR,
or host reads output data register_4
(ODR_4)
Slave CPU Master CPU
Write to ODR
Write 1 to P4DR
P4DR = 0?
Yes
No
No
Yes
All bytes
transferred?
HIRQ output high
HIRQ output low
Interrupt initiation
ODR read
Hardware operations
Software operations
Figure 18.3 HIRQ Output Flowchart (Example of Channels 1 and 2)