Datasheet

Section 18 Host Interface X-Bus Interface (XBS)
Rev. 3.00 Mar 21, 2006 page 516 of 788
REJ09B0300-0300
• HICR2
R/W
Bit Bit Name
Initial
Value
Slave Host Description
7 to 3  All 1  Reserved
These bits are always read as 1, and cannot be
modified.
2IBFIE40 R/W Input Data Register Full Interrupt Enable 4
Enables or disables the IBF4 interrupt to the
internal CPU.
0: Input data register (IDR_4) reception
completed interrupt request disabled
1: Input data register (IDR_4) reception
completed interrupt request enabled
1IBFIE30 R/W Input Data Register Full Interrupt Enable 3
Enables or disables the IBF3 interrupt to the
internal CPU.
0: Input data register (IDR_3) reception
completed interrupt request disabled
1: Input data register (IDR_3) reception
completed interrupt request enabled
0  0  Reserved
The initial value should not be changed.