Datasheet

Section 17 Keyboard Buffer Controller

Rev. 3.00 Mar 21, 2006 page 500 of 788

REJ09B0300-0300

2891011

KCLK

(pin state)

KCLK

(output)

KCLK

(input)

Start bit

Parity bit Stop bit

I/O inhibit

Receive

completed

notification

[1] [2] [3] [4] [5] [6] [7] [8]

Figure 17.6 Transmit Timing

17.4.3 Receive Abort

This LSI (system side) can forcibly abort transmission from the device connected to it (keyboard

side) in the event of a protocol error, etc. In this case, the system holds the clock low. During

reception, the keyboard also outputs a clock for synchronization, and the clock is monitored when

the keyboard output clock is high. If the clock is low at this time, the keyboard judges that there is

an abort request from the system, and data transmission from the keyboard is aborted. Thus the

system can abort reception by holding the clock low for a certain period. A sample receive abort

processing flowchart is shown in figure 17.7, and the receive abort timing in figure 17.8.