Datasheet

Section 17 Keyboard Buffer Controller
Rev. 3.00 Mar 21, 2006 page 489 of 788
REJ09B0300-0300
Section 17 Keyboard Buffer Controller
This LSI has three on-chip keyboard buffer controller channels. The keyboard buffer controller is
provided with functions conforming to the PS/2 interface specifications.
Data transfer using the keyboard buffer controller employs a data line (KD) and a clock line
(KCLK), providing economical use of connectors, board surface area, etc. Figure 17.1 shows a
block diagram of the keyboard buffer controller.
17.1 Features
• Conforms to PS/2 interface specifications
• Direct bus drive (via the KCLK and KD pins)
• Interrupt sources: on completion of data reception and on detection of clock edge
• Error detection: parity error and stop bit monitoring
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