Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 470 of 788
REJ09B0300-0300
SCL
SDA
IRIC
User processing
Clear IRIC
187
412387
When FS = 1 and FSX = 1 (clocked synchronous serial format)
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception
SCL
SDA
IRIC
User processing
Clear IRIC Clear IRICWrite to ICDR (transmit)
or read from ICDR (receive)
872143
187
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception
Figure 16.28 IRIC Setting Timing and SCL Control (3)
16.4.8 Automatic Switching from Formatless Mode to I
2
C Bus Format
Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC_0
operating mode. Switching from formatless mode to the I
2
C bus format (slave mode) is performed
automatically when a falling edge is detected on the SCL pin.
The following four preconditions are necessary for this operation:
• A common data pin (SDA) for formatless and I
2
C bus format operation
• Separate clock pins for formatless operation (VSYNCI) and I
2
C bus format operation (SCL)
• A fixed 1 level for the SCL pin during formatless operation (the SCL pin does not output a low
level)