Datasheet

Section 16 I
2
C Bus Interface (IIC) (Optional)
Rev. 3.00 Mar 21, 2006 page 461 of 788
REJ09B0300-0300
SDA
(master output)
SDA
(slave output)
21436587989
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 0
ICDRF
ICDRS
ICDRR
IRIC
SCL
(master output)
SCL
(slave output)
[8] IRIC clear
[12] IRIC clear
[9] Set ACKB=1
[5] ICDR read (
Data (n- 1))
[10] ICDR read
(
Data (n ))
User processing
Data (n )
Data (n- 1)
Data (n-2 )
[6] [6]
[11]
A A
Stop condition generation
[7] SCL is fixed low until ICDR is read
[7] SCL is fixed low until ICDR is read
Data (n- 1)
Data (n )
Data (n )
[8] IRIC clear
Data (n- 1)
Figure 16.20 Example of Slave Receive Mode Operation Timing (2)
(MLS = 0, HNDS= 1)
Continuous Receive Operation:
Figure 16.21 shows the sample flowchart for the operations in slave receive mode (HNDS = 0).