Datasheet

Rev. 3.00 Mar 21, 2006 page xl of liv
Figure 7.4 DTC Operation Flowchart ................................................................................... 155
Figure 7.5 Memory Mapping in Normal Mode..................................................................... 156
Figure 7.6 Memory Mapping in Repeat Mode...................................................................... 157
Figure 7.7 Memory Mapping in Block Transfer Mode......................................................... 158
Figure 7.8 Chain Transfer Operation .................................................................................... 159
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)................ 160
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2) ........................................................................................... 161
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)......................................... 161
Section 9 8-Bit PWM Timer (PWM)
Figure 9.1 Block Diagram of PWM Timer ........................................................................... 232
Figure 9.2 Example of Additional Pulse Timing (when Upper 4 Bits of PWDR = 1000) .... 240
Section 10 14-Bit PWM Timer (PWMX)
Figure 10.1 PWM (D/A) Block Diagram................................................................................ 243
Figure 10.2 PWM D/A Operation ........................................................................................... 251
Figure 10.3 Output Waveform (OS = 0, DADR Corresponds to T
L
) ...................................... 253
Figure 10.4 Output Waveform (OS = 1, DADR Corresponds to T
H
) ...................................... 254
Figure 10.5 D/A Data Register Configuration when CFS = 1................................................. 254
Figure 10.6 Output Waveform when DADR = H'0207 (OS = 1)............................................ 255
Section 11 16-Bit Free-Running Timer (FRT)
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer.................................................... 260
Figure 11.2 Example of Pulse Output ..................................................................................... 271
Figure 11.3 Increment Timing with Internal Clock Source..................................................... 272
Figure 11.4 Increment Timing with External Clock Source ................................................... 272
Figure 11.5 Timing of Output Compare A Output.................................................................. 273
Figure 11.6 Clearing of FRC by Compare-Match A Signal.................................................... 273
Figure 11.7 Input Capture Input Signal Timing (Usual Case)................................................. 274
Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read)................. 274
Figure 11.9 Buffered Input Capture Timing............................................................................ 275
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)..................................................... 275
Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ................ 276
Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting................................ 277
Figure 11.13 Timing of Overflow Flag (OVF) Setting ............................................................. 277
Figure 11.14 OCRA Automatic Addition Timing..................................................................... 278
Figure 11.15 Timing of Input Capture Mask Signal Setting..................................................... 278
Figure 11.16 Timing of Input Capture Mask Signal Clearing................................................... 279
Figure 11.17 FRC Write-Clear Conflict.................................................................................... 280
Figure 11.18 FRC Write-Increment Conflict ............................................................................ 281