Datasheet

Section 12 8-Bit Timer (TMR)
Rev. 3.00 Mar 21, 2006 page 310 of 788
REJ09B0300-0300
12.9 Usage Notes
12.9.1 Conflict between TCNT Write and Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle as shown in figure
12.14, clearing takes priority, so that the counter is cleared and the write is not performed.
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 12.14 Conflict between TCNT Write and Clear