Datasheet

Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Mar 21, 2006 page 280 of 788
REJ09B0300-0300
11.7 Usage Notes
11.7.1 Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 11.17 shows the timing for this type of
conflict.
φ
Address FRC address
Internal write signal
Counter clear signal
FRC N H'0000
T
1
T
2
Write cycle of FRC
Figure 11.17 FRC Write-Clear Conflict