Datasheet

Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Mar 21, 2006 page 275 of 788
REJ09B0300-0300
Input capture
signal
φ
FTIA
FRC
ICRA
ICRC
n n + 1 N + 1N
Mn
mM
n
M
N
n
Figure 11.9 Buffered Input Capture Timing
Even when ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICICE bit is set at this time, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however. In buffered input capture, if either set of two registers to which data
will be transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input capture
input signal arrives, input capture is delayed by one system clock (φ). Figure 11.10 shows the
timing when BUFEA = 1.
Input capture
signal
FTIA
φ
T
1
T
2
CPU read cycle of ICRA or ICRC
Figure 11.10 Buffered Input Capture Timing (BUFEA = 1)