Datasheet

Section 11 16-Bit Free-Running Timer (FRT)
Rev. 3.00 Mar 21, 2006 page 272 of 788
REJ09B0300-0300
11.5 Operation Timing
11.5.1 FRC Increment Timing
Figure 11.3 shows the FRC increment timing with an internal clock source. Figure 11.4 shows the
increment timing with an external clock source. The pulse width of the external clock signal must
be at least 1.5 system clocks (φ). The counter will not increment correctly if the pulse width is
shorter than 1.5 system clocks (φ).
φ
Internal clock
FRC input
clock
FRC N – 1 N + 1N
Figure 11.3 Increment Timing with Internal Clock Source
φ
External clock
input pin
FRC input
clock
FRC N + 1N
Figure 11.4 Increment Timing with External Clock Source