Datasheet

Section 8 I/O Ports
Rev. 3.00 Mar 21, 2006 page 205 of 788
REJ09B0300-0300
8.11.1 Port A Data Direction Register (PADDR)
PADDR specifies input or output for the pins of port A on a bit-by-bit basis.
Bit Bit Name Initial Value R/W Description
7 PA7DDR 0 W
6 PA6DDR 0 W
5 PA5DDR 0 W
4 PA4DDR 0 W
3 PA3DDR 0 W
2 PA2DDR 0 W
1 PA1DDR 0 W
0 PA0DDR 0 W
In mode 1, 2 (EXPE = 0), or 3:
The corresponding port A pins are output ports
when PADDR bits are set to 1, and input ports
when cleared to 0.
In mode 2 (EXPE = 1):
The corresponding port A pins are address output
when PADDR bits are set to 1, and input ports
when cleared to 0. The port A pins changes from
the address I/O ports to output ports by setting
the IOSE bit to 1.
PA7 to PA2 pins are used as the keyboard buffer
controller I/O pins by setting the KBIOE bit to 1
regardless of the operating mode, while the I/O
direction according to PA7DDR to PA2DDR is
ignored.
PADDR has the same address as PAPIN, if read,
port A status is returned.
8.11.2 Port A Output Data Register (PAODR)
PAODR stores output data for port A.
Bit Bit Name Initial Value R/W Description
7 PA7ODR 0 R/W
6 PA6ODR 0 R/W
5 PA5ODR 0 R/W
4 PA4ODR 0 R/W
3 PA3ODR 0 R/W
2 PA2ODR 0 R/W
1 PA1ODR 0 R/W
0 PA0ODR 0 R/W
PAODR can always be read or written to,
regardless of the contents of PADDR.