Datasheet

Section 8 I/O Ports
Rev. 3.00 Mar 21, 2006 page 201 of 788
REJ09B0300-0300
8.10.2 Port 9 Data Register (P9DR)
P9DR stores output data for the port 9 pins.
Bit Bit Name Initial Value R/W Description
7 P97DR 0 R/W
6 P96DR Undefined
*
R
5 P95DR 0 R/W
4 P94DR 0 R/W
3 P93DR 0 R/W
2 P92DR 0 R/W
1 P91DR 0 R/W
0 P90DR 0 R/W
With the exception of P96, if a port 9 read is
performed while P9DDR bits are set to 1, the
P9DR values are read directly, regardless of the
actual pin states. If a port 9 read is performed
while P9DDR bits are cleared to 0, the pin states
are read.
For P96, the pin state is always read.
Note: * The initial value of bit 6 is determined according to the P96 pin state.
8.10.3 Pin Functions
• P97/WAIT/SDA0
The pin function is switched as shown below according to the combination of operating mode,
the WMS1 bit in WSCR, the ICE bit in ICCR of IIC_0, and the P97DDR bit.
Operating
Mode
Modes 1, 2, 3 (EXPE = 1) Modes 2, 3 (EXPE = 0)
WMS1 0 1 —
ICE 0 1 — 0 1
P97DDR 0 1 — — 0 1 —
Pin Function P97 input
pin
P97
output pin
SDA0 I/O
pin
WAIT
input
pin
P97 input
pin
P97
output pin
SDA0 I/O
pin
Note: When this pin is set as the P97 output pin, it is an NMOS push-pull output. SDA0 is an
NMOS open-drain output, and has direct bus drive capability.