Datasheet

Rev. 3.00 Mar 21, 2006 page xxiii of liv
5.3.4 IRQ Sense Control Registers (ISCRH, ISCRL)................................................... 95
5.3.5 IRQ Enable Register (IER) .................................................................................. 96
5.3.6 IRQ Status Register (ISR).................................................................................... 96
5.3.7 Keyboard Matrix Interrupt Mask Registers (KMIMRA, KMIMR) and
Wake-Up Event Interrupt Mask Register (WUEMRB) ....................................... 97
5.4 Interrupt Sources............................................................................................................... 100
5.4.1 External Interrupts ............................................................................................... 100
5.4.2 Internal Interrupts................................................................................................. 102
5.5 Interrupt Exception Handling Vector Table...................................................................... 102
5.6 Interrupt Control Modes and Interrupt Operation............................................................. 105
5.6.1 Interrupt Control Mode 0..................................................................................... 105
5.6.2 Interrupt Control Mode 1..................................................................................... 107
5.6.3 Interrupt Exception Handling Sequence .............................................................. 110
5.6.4 Interrupt Response Times .................................................................................... 112
5.6.5 DTC Activation by Interrupt................................................................................ 113
5.7 Address Break................................................................................................................... 115
5.7.1 Features................................................................................................................ 115
5.7.2 Block Diagram..................................................................................................... 115
5.7.3 Operation ............................................................................................................. 116
5.7.4 Usage Notes ......................................................................................................... 116
5.8 Usage Notes ...................................................................................................................... 118
5.8.1 Conflict between Interrupt Generation and Disabling ......................................... 118
5.8.2 Instructions that Disable Interrupts...................................................................... 119
5.8.3 Interrupts during Execution of EEPMOV Instruction.......................................... 119
5.8.4 Setting on Product Incorporating DTC................................................................ 119
5.8.5 IRQ Status Register (ISR).................................................................................... 120
Section 6 Bus Controller (BSC)...................................................................................... 121
6.1 Features............................................................................................................................. 121
6.2 Input/Output Pins.............................................................................................................. 123
6.3 Register Descriptions........................................................................................................ 123
6.3.1 Bus Control Register (BCR) ................................................................................ 124
6.3.2 Wait State Control Register (WSCR) .................................................................. 125
6.4 Bus Control....................................................................................................................... 126
6.4.1 Bus Specifications................................................................................................ 126
6.4.2 Advanced Mode................................................................................................... 127
6.4.3 Normal Mode....................................................................................................... 127
6.4.4 I/O Select Signals................................................................................................. 128
6.5 Basic Bus Interface ........................................................................................................... 129
6.5.1 Data Size and Data Alignment............................................................................. 129
6.5.2 Valid Strobes........................................................................................................ 130