Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 143 of 788
REJ09B0300-0300
T
1
Address bus
φ
Bus cycle A
Data bus
T
2
T
3
T
1
T
2
Bus cycle B
Long output floating time
Data collision
(a) No idle cycle insertion
T
1
Address bus
φ
Bus cycle A
Data bus
T
2
T
3
T
I
T
1
Bus cycle B
(b) Idle cycle insertion
T
2
HWR, LWR HWR, LWR
RD RD
Figure 6.16 Examples of Idle Cycle Operation
Table 6.5 shows the pin states in an idle cycle.
Table 6.5 Pin States in Idle Cycle
Pins Pin State
A23 to A0, IOS Contents of immediately following bus cycle
D15 to D0 High impedance
AS High
RD High
HWR, LWR High