Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 138 of 788
REJ09B0300-0300
Bus cycle
T
1
T
2
Address bus
φ
AS
/
IOS
(IOSE = 0)
RD
D15 to D8
Valid
D7 to D0
Valid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
Valid
Write
T
3
AS
/
IOS
(IOSE = 1)
Figure 6.12 Bus Timing for 16-Bit, 3-State Access Space (Word Access)
