Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 128 of 788
REJ09B0300-0300
RAME bit in SYSCR is set to 1, and disabled and specified as the external address space when the
RAME bit is cleared to 0.
6.4.4 I/O Select Signals
The LSI can output I/O select signals (IOS); the signal is driven low when the corresponding
external address space is accessed. Figure 6.2 shows an example of IOS signal output timing.
Bus cycle
T
1
T
2
Address bus
φ
IOS
T
3
External addresses selected by IOS
Figure 6.2 IOS
IOSIOS
IOS Signal Output Timing
Enabling or disabling IOS signal output is performed by the IOSE bit in SYSCR. In extended
mode, the IOS pin functions as an AS pin by a reset. To use this pin as an IOS pin, set the IOSE
bit to 1. For details, refer to section 8, I/O Ports.
The address ranges of the IOS signal output can be specified by the IOS1 and IOS0 bits in BCR,
as shown in table 6.3.
Table 6.3 Address Range for IOS
IOSIOS
IOS Signal Output
IOS1 IOS0 IOS
IOSIOS
IOS Signal Output Range
0 H'(FF)F000 to H'(FF)F03F
0
1 H'(FF)F000 to H'(FF)F0FF
0 H'(FF)F000 to H'(FF)F3FF1
1 H'(FF)F000 to H'(FF)F7FF (Initial value)