Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 21, 2006 page 121 of 788
REJ09B0300-0300
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the bus width and the number of
access states of the external address space. The BSC also has a bus arbitration function, and
controls the operation of the internal bus masters – CPU, and data transfer controller (DTC).
6.1 Features
• Basic bus interface
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• Burst ROM interface
A burst ROM interface can be set for basic expansion areas
1-state access or 2-state access can be selected for burst access
• Idle cycle insertion
An idle cycle can be inserted for external write cycles immediately after external read cycles
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastership between the CPU and DTC
BSCS20AA_000020020700