Datasheet

Section 5 Interrupt Controller
Rev. 3.00 Mar 21, 2006 page 96 of 788
REJ09B0300-0300
5.3.5 IRQ Enable Register (IER)
IER controls the enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQn Enable (n = 7 to 0)
The IRQn interrupt request is enabled when this
bit is 1.
5.3.6 IRQ Status Register (ISR)
The ISR register is a flag register that indicates the status of IRQ7 to IRQ0 interrupt requests.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R/(W)
*
2
R/(W)
*
2
R/(W)
*
2
R/(W)
*
2
R/(W)
*
2
R/(W)
*
2
R/(W)
*
2
R/(W)
*
2
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing conditions]
• When reading IRQnF flag when IRQnF = 1,
then writing 0 to IRQnF flag
• When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high (n = 7 to 0)
*
1
• When IRQn interrupt exception handling is
executed when falling-edge, rising-edge, or
both-edge detection is set
*
1
Notes: 1. When a product, in which a DTC is incorporated, is used, the corresponding flag bit is
not automatically cleared even when exception handing is executed. For details, refer to
section 5.8.4, Setting on a Product Incorporating DTC.
2. Only 0 can be written, for flag clearing.