Datasheet

Section 2 CPU
Rev. 4.00 Sep 27, 2006 page 53 of 1130
REJ09B0327-0400
2.6.2 Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2000 CPU
can use.
Table 2.2 Combinations of Instructions and Addressing Modes
Addressing Modes
Function Instruction
#xx Rn @ERn @(d:16,ERn) @(d:32, ERn) @–ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8, PC) @(d:16, PC) @@aa:8 —
MOV BWL BWL BWL BWL BWL BWL B BWL — BWL ————
POP, PUSH —————————————WL
LDM
*
3
, STM
*
3
————————————— L
Data
transfer
MOVFPE
*
1
,
MOVTPE
*
1
——————— B ——————
ADD, CMP BWL BWL ————————————
SUB WL BWL ————————————
ADDX, SUBX B B ————————————
ADDS, SUBS — L ————————————
INC, DEC — BWL ————————————
DAA, DAS — B ————————————
MULXU,
DIVXU
— BW ————————————
MULXS,
DIVXS
— BW ————————————
NEG — BWL ————————————
EXTU, EXTS — WL ————————————
Arithmetic
operations
TAS
*
2
—— B ———————————
AND, OR,
XOR
BWL BWL ————————————Logic
operations
NOT — BWL ————————————
Shift — BWL ————————————
Bit-manipulation — BB——— BB— B ————
Bcc, BSR —————————— ——
JMP, JSR ———————— ——— —
Branch
RTS —————————————