Datasheet

Section 26 Electrical Characteristics
Rev. 4.00 Sep 27, 2006 page 904 of 1130
REJ09B0327-0400
Condition A Condition B Condition C
20 MHz 16 MHz 10 MHz
Item Symbol Min Max Min Max Min Max Unit
Test
Conditions
TMR Timer output
delay time
t
TMOD
— 50 — 50 — 100 ns Figure
26.18
Timer reset input
setup time
t
TMRS
30
—
30
— 50 — Figure
26.20
Timer clock input
setup time
t
TMCS
30 — 30 — 50 — Figure
26.19
Single
edge
t
TMCWH
1.5 — 1.5 — 1.5
—
t
cyc
Timer
clock
pulse
width
Both
edges
t
TMCWL
2.5 — 2.5 — 2.5 —
PWMX Pulse output
delay time
t
PWOD
— 50 — 50 — 100 ns Figure
26.21
SCI Asynchro-
nous
t
Scyc
4— 4— 4— t
cyc
Figure
26.22
Input
clock
cycle
Synchro-
nous
6— 6— 6—
Input clock pulse
width
t
SCKW
0.4 0.6 0.4 0.6 0.4 0.6 t
Scyc
Input clock rise
time
t
SCKr
— 1.5 — 1.5 — 1.5 t
cyc
Input clock fall
time
t
SCKf
— 1.5 — 1.5 — 1.5
Transmit data
delay time
(synchronous)
t
TXD
— 50 — 50 — 100 ns Figure
26.23
Receive data setup
time (synchronous)
t
RXS
50 — 50 — 100 — ns
Receive data hold
time (synchronous)
t
RXH
50 — 50 — 100 — ns
A/D
conver-
ter
Trigger input setup
time
t
TRGS
30 — 30 — 50 — ns Figure
26.24
WDT RESO output delay
time
t
RESD
— 100 — 120 — 200 ns Figure
26.25
RESO output pulse
width
t
RESOW
132 — 132 — 132 — t
cyc
Note: * Only supporting modules that can be used in subclock operation