Datasheet

Section 25 Power-Down State

Rev. 4.00 Sep 27, 2006 page 756 of 1130

REJ09B0327-0400

Table 25.4 MSTP Bits and Corresponding On-Chip Supporting Modules

MSTPCRH MSTP15 —

MSTP14

Data transfer controller (DTC)

MSTP13 16-bit free-running timer (FRT)

MSTP12 8-bit timer (TMR0, TMR1)

MSTP11 8-bit PWM timer (PWM), 14-bit PWM timer (PWMX)

MSTP10 D/A converter

MSTP9 A/D converter

MSTP8 8-bit timers (TMRX, TMRY), timer connection

MSTPCRL MSTP7 Serial communication interface 0 (SCI0)

MSTP6 Serial communication interface 1 (SCI1)

MSTP5 Serial communication interface 2 (SCI2)

MSTP4

C bus interface (IIC) channel 0 (option)

MSTP3

C bus interface (IIC) channel 1 (option)

MSTP2 Host interface (HIF), keyboard matrix interrupt mask register (KMIMR,

KMIMRA), port 6 MOS pull-up control register (KMPCR), keyboard

buffer controller (PS2)

MSTP1

—

MSTP0

—

Notes: Do not set bit 15 to 1. Bits 1 and 0 can be read or written to, but do not affect operation.

* Must be set to 1 in the H8S/2144 Group and H8S/2147N.

25.5.2 Usage Note

If there is conflict between DTC module stop mode setting and a DTC bus request, the bus request

has priority and the MSTP bit will not be set to 1.

Write 1 to the MSTP bit again after the DTC bus cycle.

When using the H8S/2144 Group and H8S/2147N, the MSTP bits for nonexistent modules must

be set to 1.