Datasheet

Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 752 of 1130
REJ09B0327-0400
For details, see the description of Clock Select 2 to 0 in section 14.2.2, Timer Control/Status
Register (TCSR).
Bit 4
PSS Description
0 TCNT counts φ-based prescaler (PSM) divided clock pulses
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode or software standby mode (Initial value)
1 TCNT counts φSUB-based prescaler (PSM) divided clock pulses
When a SLEEP instruction is executed in high-speed mode or medium-speed mode,
a transition is made to sleep mode, watch mode
*
, or subactive mode
*
When a SLEEP instruction is executed in subactive mode, a transition is made to
subsleep mode, watch mode, or high-speed mode
Note: * When a transition is made to watch mode or subactive mode, high-speed mode must
be set.
25.2.4 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTRCRH and MSTPCRL Bits 7 to 0—Module Stop (MSTP 15 to MSTP 0): These bits
specify module stop mode. See table 25.4 for the method of selecting on-chip supporting modules.
MSTPCRH, MSTPCRL
Bits 7 to 0
MSTP15 to MSTP0 Description
0 Module stop mode is cleared (Initial value of MSTP15, MSTP14)
1 Module stop mode is set (Initial value of MSTP13 to MSTP0)