Datasheet

Section 25 Power-Down State
Rev. 4.00 Sep 27, 2006 page 747 of 1130
REJ09B0327-0400
25.1.1 Register Configuration
The power-down state is controlled by the SBYCR, LPWRCR, TCSR (WDT1), and MSTPCR
registers. Table 25.3 summarizes these registers.
Table 25.3 Power-Down State Registers
Name Abbreviation R/W Initial Value Address
*
1
Standby control register SBYCR R/W H'00 H'FF84
*
2
Low-power control register LPWRCR R/W H'00 H'FF85
*
2
Timer control/status register
(WDT1)
TCSR R/W H'00 H'FFEA
Module stop control register MSTPCRH R/W H'3F H'FF86
*
2
MSTPCRL R/W H'FF H'FF87
*
2
Notes: 1. Lower 16 bits of the address.
2. Some power down state registers are assigned to the same address as other registers.
In this case, register selection is performed by the FLSHE bit in the serial timer control
register (STCR).
25.2 Register Descriptions
25.2.1 Standby Control Register (SBYCR)
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
—
0
—
0
SCK0
0
R/W
2
SCK2
0
R/W
1
SCK1
0
R/W
Bit
Initial value
Read/Write
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.