Datasheet

Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 741 of 1130
REJ09B0327-0400
24.9 Clock Selection Circuit
This circuit selects the system clock used in the MCU.
The clock signal generated in the EXTAL/XTAL pin oscillator is selected as the system clock
when MCU is returned from high-speed mode, medium-speed mode, sleep mode, reset state, or
standby mode.
In sub-active mode, sub-sleep mode, and watch mode, the sub-clock signal input from EXCL pin
is selected as the system clock. In these modes, modules such as CPU, TMR0, TMR1, WDT0,
WDT1, and I/O ports operate on the φ SUB clock. The count clock for each timer is a clock
obtained by driving the φ SUB clock.