Datasheet

Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 738 of 1130
REJ09B0327-0400
external clock output settling delay time (t
DEXT
). As the clock signal output is not fixed during the
t
DEXT
period, the reset signal should be driven low to maintain the reset state.
Table 24.5 External Clock Output Settling Delay Time
Conditions: V
CC
= 2.7 V to 5.5 V, AV
CC
= 2.7 V to 5.5 V, V
SS
= AV
SS
= 0 V
Item Symbol Min Max Unit Notes
External clock
output settling
delay time
t
DEXT
*
500 — µs Figure 24.7
Note: * t
DEXT
includes RES pulse width (t
RESW
).
t
DEXT
*
RES
(internal or external)
EXTAL
STBY
V
CC
2.7V
V
IH
φ
Note: * t
DEXT
includes RES pulse width (t
RESW
).
Figure 24.7 External Clock Output Settling Delay Timing