Datasheet

Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 737 of 1130
REJ09B0327-0400
External Clock
The external clock signal should have the same frequency as the system clock (φ).
Table 24.4 and figure 24.6 show the input conditions for the external clock.
Table 24.4 External Clock Input Conditions
V
CC
= 2.7 to 5.5 V V
CC
= 5.0 V ±10%
Item Symbol Min Max Min Max Unit Test Conditions
External clock
input low pulse
width
t
EXL
40 — 20 — ns Figure 24.6
External clock
input high pulse
width
t
EXH
40 — 20 — ns
External clock
rise time
t
EXr
— 10 — 5ns
External clock
fall time
t
EXf
— 10 — 5ns
t
CL
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHz Figure 26.5Clock low
pulse width
80 — 80 — ns φ < 5 MHz
t
CH
0.4 0.6 0.4 0.6 t
cyc
φ ≥ 5 MHzClock high
pulse width
80 — 80 — ns φ < 5 MHz
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
× 0.5
EXTAL
Figure 24.6 External Clock Input Timing
Table 24.5 shows the external clock output settling delay time, and figure 24.7 shows the external
clock output settling delay timing. The oscillator and duty adjustment circuit have a function for
adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock
signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the