Datasheet

Section 24 Clock Pulse Generator
Rev. 4.00 Sep 27, 2006 page 733 of 1130
REJ09B0327-0400
Bit 2 Bit 1 Bit 0
SCK2 SCK1 SCK0 Description
0 0 0 Bus master is in high-speed mode (Initial value)
1 Medium-speed clock is φ/2
1 0 Medium-speed clock is φ/4
1 Medium-speed clock is φ/8
1 0 0 Medium-speed clock is φ/16
1 Medium-speed clock is φ/32
1——
24.2.2 Low-Power Control Register (LPWRCR)
7
DTON
0
R/W
6
LSON
0
R/W
5
NESEL
0
R/W
4
EXCLE
0
R/W
3
—
0
—
0
—
0
—
2
—
0
—
1
—
0
—
Bit
Initial value
Read/Write
LPWRCR is an 8-bit readable/writable register that performs power-down mode control.
Only bit 4 is described here. For a description of the other bits, see section 25.2.2, Low-Power
Control Register (LPWRCR).
LPWRCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 4—Subclock Input Enable (EXCLE): Controls subclock input from the EXCL pin.
Bit 4
EXCLE Description
0 Subclock input from EXCL pin is disabled (Initial value)
1 Subclock input from EXCL pin is enabled