Datasheet

Section 23 ROM (H8S/2148 F-ZTAT A-Mask Version, H8S/2147 F-ZTAT A-Mask Version, H8S/2144 F-ZTAT A-Mask Version)
Rev. 4.00 Sep 27, 2006 page 694 of 1130
REJ09B0327-0400
23.4.4 Pin Configuration
The flash memory is controlled by means of the pins shown in table 23.3.
Table 23.3 Flash Memory Pins
Pin Name Abbreviation I/O Function
Reset RES Input Reset
Mode 1 MD1 Input Sets MCU operating mode
Mode 0 MD0 Input Sets MCU operating mode
Port 92 P92 Input Sets MCU operating mode when MD1 = MD0 = 0
Port 91 P91 Input Sets MCU operating mode when MD1 = MD0 = 0
Port 90 P90 Input Sets MCU operating mode when MD1 = MD0 = 0
Transmit data TxD1 Output Serial transmit data output
Receive data RxD1 Input Serial receive data input
23.4.5 Register Configuration
The registers used to control the on-chip flash memory when enabled are shown in table 23.4.
In order for these registers to be accessed, the FLSHE bit must be set to 1 in STCR.
Table 23.4 Flash Memory Registers
Register Name Abbreviation R/W Initial Value Address
*
1
Flash memory control register 1 FLMCR1
*
5
R/W
*
3
H'80 H'FF80
*
2
Flash memory control register 2 FLMCR2
*
5
R/W
*
3
H'00
*
4
H'FF81
*
2
Erase block register 1 EBR1
*
5
R/W
*
3
H'00
*
4
H'FF82
*
2
Erase block register 2 EBR2
*
5
R/W
*
3
H'00
*
4
H'FF83
*
2
Serial/timer control register STCR R/W H'00 H'FFC3
Notes: 1. Lower 16 bits of the address.
2. Flash memory registers share addresses with other registers. Register selection is
performed by the FLSHE bit in the serial/timer control register (STCR).
3. In modes in which the on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
4. When the SWE bit in FLMCR1 is not set, these registers are initialized to H'00.
5. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are valid
for these registers, the access requiring 2 states.