Datasheet

Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 651 of 1130
REJ09B0327-0400
Bit 0—Program (P): Selects program mode transition or clearing. Do not set the SWE, PSU,
ESU, EV, PV, or E bit at the same time.
Bit 0
P Description
0 Program mode cleared (Initial value)
1 Transition to program mode
[Setting condition]
When SWE = 1, and PSU = 1
22.5.2 Flash Memory Control Register 2 (FLMCR2)
Bit 76543210
FLER —————ESU PSU
Initial value00000000
Read/Write R —————R/W R/W
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory program/erase
protection (error protection) and performs setup for flash memory program/erase mode. FLMCR2
is initialized to H'00 by a reset, and in hardware standby mode. The ESU and PSU bits are cleared
to 0 in software standby mode, subactive mode, subsleep mode, and watch mode.
When on-chip flash memory is disabled, a read will return H'00, and writes are invalid.
Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.