Datasheet

Section 22 ROM (Mask ROM Version, H8S/2148 F-ZTAT, H8S/2147N F-ZTAT, H8S/2144 F-ZTAT, and H8S/2142 F-ZTAT)
Rev. 4.00 Sep 27, 2006 page 640 of 1130
REJ09B0327-0400
22.1.2 Register Configuration
This group on-chip ROM is controlled by the operating mode and register MDCR. The register
configuration is shown in table 22.1.
Table 22.1 ROM Register
Register Name Abbreviation R/W Initial Value Address
*
Mode control register MDCR R/W Undefined
Depends on the operating mode
H'FFC5
Note: * Lower 16 bits of the address.
22.2 Register Descriptions
22.2.1 Mode Control Register (MDCR)
Bit
Initial value
Read/Write
7
EXPE
—*
R/W
*
6
—
0
—
5
—
0
—
4
—
0
—
3
—
0
—
0
MDS0
—*
R
2
—
0
—
1
MDS1
—*
R
Note: * Determined by the MD1 and MD0 pins.
MDCR is an 8-bit register used to set this group operating mode and monitor the current operating
mode.
The EXPE bit is initialized in accordance with the mode pin states by a reset and in hardware
standby mode.
Bit 7—Expanded Mode Enable (EXPE): Sets expanded mode. In mode 1, EXPE is fixed at 1
and cannot be modified. In modes 2 and 3, EXPE has an initial value of 0 and can be read or
written.
Bit 7
EXPE Description
0 Single-chip mode selected
1 Expanded mode selected