Datasheet

Section 21 RAM
Rev. 4.00 Sep 27, 2006 page 636 of 1130
REJ09B0327-0400
21.1.2 Register Configuration
The on-chip RAM is controlled by SYSCR. Table 21.1 shows the register configuration.
Table 21.1 Register Configuration
Name Abbreviation R/W Initial Value Address
*
System control register SYSCR R/W H'09 H'FFC4
Note: * Lower 16 bits of the address.
21.2 System Control Register (SYSCR)
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
Bit
Initial value
Read/Write
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled
1 On-chip RAM is enabled (Initial value
)