Datasheet

Section 20 A/D Converter
Rev. 4.00 Sep 27, 2006 page 629 of 1130
REJ09B0327-0400
Table 20.4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Item Symbol Min Typ Max Min Typ Max
A/D conversion start delay t
D
10 — 17 6 — 9
Input sampling time t
SPL
— 63 ——31 —
A/D conversion time t
CONV
259 — 266 131 — 134
Note: Values in the table are the number of states.
20.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit is set to 1 by software. Figure 20.6 shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 20.6 External Trigger Input Timing
20.5 Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.