Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 595 of 1130
REJ09B0327-0400
18.2.7 Module Stop Control Register (MSTPCR)
7
MSTP15
0
R/W
Bit
Initial value
Read/Write
6
MSTP14
0
R/W
5
MSTP13
1
R/W
4
MSTP12
1
R/W
3
MSTP11
1
R/W
2
MSTP10
1
R/W
1
MSTP9
1
R/W
0
MSTP8
1
R/W
7
MSTP7
1
R/W
6
MSTP6
1
R/W
5
MSTP5
1
R/W
4
MSTP4
1
R/W
3
MSTP3
1
R/W
2
MSTP2
1
R/W
1
MSTP1
1
R/W
0
MSTP0
1
R/W
MSTPCRH MSTPCRL
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP2 bit is set to 1, the host interface halts and enters module stop mode. See section
25.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 2—Module Stop (MSTP2): Specifies host interface module stop mode.
MSTPCRL
Bit 2
MSTP2 Description
0 Host interface module stop mode is cleared
1 Host interface module stop mode is set (Initial value)
18.3 Operation
18.3.1 Host Interface Activation
The HIF (slave mode) is activated by setting the HI12E bit (bit 0) in SYSCR2 to 1 in single-chip
mode. When the HIF (slave mode) is activated, all related I/O ports (data port 3, control ports 8
and 9, and host interrupt request port 4) become dedicated host interface ports. Setting the CS3E
bit and CS4E bit to 1 enables the number of HIF channels to be extended to a four, and makes the
channel 3 and 4 related I/O port (part of port B for control and host interrupt requests) a dedicated
host interface port.
Table 18.4 shows HIF host interface channel selection and pin operation.