Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 592 of 1130
REJ09B0327-0400
18.2.4 Input Data Register 1 (IDR1)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
IDR7
—
R
W
6
IDR6
—
R
W
5
IDR5
—
R
W
4
IDR4
—
R
W
3
IDR3
—
R
W
0
IDR0
—
R
W
2
IDR2
—
R
W
1
IDR1
—
R
W
IDR1 is an 8-bit read-only register to the slave processor, and an 8-bit write-only register to the
host processor. When CSn (n = 1 to 4) is low, information on the host data bus is written into
IDRn at the rising edge of IOW. The HA0 state is also latched into the C/D bit in STRn to indicate
whether the written information is a command or data.
The initial values of IDR1 after a reset and in standby mode are undetermined.
18.2.5 Output Data Register 1 (ODR)
Bit
Initial value
Slave Read/Write
Host Read/Write
7
ODR7
—
R/W
R
6
ODR6
—
R/W
R
5
ODR5
—
R/W
R
4
ODR4
—
R/W
R
3
ODR3
—
R/W
R
0
ODR0
—
R/W
R
2
ODR2
—
R/W
R
1
ODR1
—
R/W
R
ODR1 is an 8-bit readable/writable register to the slave processor, and an 8-bit read-only register
to the host processor. The ODRn contents are output on the host data bus when HA0 is low, CSn
(n = 1 to 4) is low, and IOR is low.
The initial values of ODR1 after a reset and in standby mode are undetermined.