Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 590 of 1130
REJ09B0327-0400
18.2.3 Host Interface Control Register (HICR)
• HICR
Bit
Initial value
Slave Read/Write
Host Read/Write
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
FGA20E
0
R/W
—
2
IBFIE2
0
R/W
—
1
IBFIE1
0
R/W
—
• HICR2
Bit
Initial value
Slave Read/Write
Host Read/Write
7
—
1
—
—
6
—
1
—
—
5
—
1
—
—
4
—
1
—
—
3
—
1
—
—
0
—
0
—
—
2
IBFIE4
0
R/W
—
1
IBFIE3
0
R/W
—
HICR is an 8-bit readable/writable register which controls host interface channel 1 and 2 interrupts
and the fast A20 gate function. HICR2 is an 8-bit readable/writable register which controls host
interface channel 3 and 4 interrupts. HICR and HICR2 are initialized to H'F8 by a reset and in
hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
HICR Bits 2 and 1—Input Data Register Full Interrupt Enable 2 and 1 (IBFIE2, IBFIE1)
HICR2 Bits 2 and 1—Input Data Register Full Interrupt Enable 4 and 3 (IBFIE4, IBFIE3)
These bits enable or disable the IBF1, IBF2, IBF3, and IBF4 interrupts to the internal CPU.