Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 587 of 1130
REJ09B0327-0400
18.2 Register Descriptions
18.2.1 System Control Register (SYSCR)
Bit
Initial value
Read/Write
7
CS2E
0
R/W
6
IOSE
0
R/W
5
INTM1
0
R
4
INTM0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
HIE
0
R/W
SYSCR is an 8-bit readable/writable register which controls H8S/2148 Group chip operations. Of
the host interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be
accessed when the HIE bit is set to 1. HICR2, IDR3, ODR3, STR3, IDR4, ODR4, and STR4 can
be accessed regardless of the setting of the HIE bit. The host interface CS2 and ECS2 pins are
controlled by the CS2E bit in SYSCR and the FGA20E bit in HICR. See section 3.2.2, System
Control Register (SYSCR), and section 5.2.1, System Control Register (SYSCR), for information
on other SYSCR bits. SYSCR is initialized to H'09 by a reset and in hardware standby mode.
Bit 7—CS2 Enable Bit (CS2E): Used together with the FGA20E bit in HICR to select the pin
that performs the CS2 function.
SYSCR
Bit 7
HICR
Bit 0
CS2E FGA20E Description
00CS2 pin function halted (CS2 fixed high internally) (Initial value)
1
10CS2 pin function selected for P81/CS2 pin
1 CS2 pin function selected for P90/ECS2 pin