Datasheet

Section 18 Host Interface
Rev. 4.00 Sep 27, 2006 page 584 of 1130
REJ09B0327-0400
18.1.2 Block Diagram
Figure 18.1 shows a block diagram of the host interface.
Internal interrupt signals
IBF2
IBF1
Control logic
HDB7 to HDB0
IDR3
ODR3
STR3
IDR4
ODR4
STR4
HICR2
Module data bus
Host data bus
Host
interrupt
request
Fast
A20 gate
control
Port 4, port 8, port B
Internal data bus
Bus
interface
CS1
C
S2/ECS2
CS3
CS4
IOR
IOW
HA0
HIRQ1
HIRQ11
HIRQ12
HIRQ3
HIRQ4
GA20
HIFSD
IDR1
ODR1
STR1
IDR2
ODR2
STR2
HICR
IBF4
IBF3
Legend:
IDR1:
IDR2:
ODR1:
ODR2:
STR1:
STR2:
HICR:
Input data register 1
Input data register 2
Output data register 1
Output data register 2
Status register 1
Status register 2
Host interface control register 1
IDR3:
IDR4:
ODR3:
ODR4:
STR3:
STR4:
HICR2:
Input data register 3
Input data register 4
Output data register 3
Output data register 4
Status register 3
Status register 4
Host interface control register 2
Figure 18.1 Block Diagram of Host Interface