Datasheet

Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 581 of 1130
REJ09B0327-0400
17.3.9 Usage Note
When KBIOE is 0, the internal KCLK and internal KD settings are fixed at 1.
Therefore, if the KCLK pin is low when the KBIOE bit is set to 1, the edge detection circuit
operates and the KCLK falling edge is detected.
If the KBFSEL bit and KBE bit are both 0 at this time, the KBF bit is set. Figure 17.14 shows the
timing of KBIOE setting and KCLK falling edge detection.
T1 T2
φ
KCLK (pin)
Internal KCLK
(KCLKI)
Falling edge
signal
KBIOE
KBFSEL
KBE
KBF
Figure 17.14 KBIOE Setting and KCLK Falling Edge Detection Timing