Datasheet

Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 568 of 1130
REJ09B0327-0400
17.3 Operation
17.3.1 Receive Operation
In a receive operation, both KCLK (clock) and KD (data) are outputs on the keyboard side and
inputs on the H8S/2148 Group chip (system) side. KD receives a start bit, 8 data bits (LSB-first),
an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is low. A sample
receive processing flowchart is shown in figure 17.3, and the receive timing in figure 17.4.