Datasheet

Section 17 Keyboard Buffer Controller
Rev. 4.00 Sep 27, 2006 page 565 of 1130
REJ09B0327-0400
Bit 1—Parity Error (PER): Indicates that an odd parity error has occurred.
Bit 1
PER Description
0 [Clearing condition] (Initial value)
Read PER when PER =1, then write 0 in PER
1 [Setting condition]
When an odd parity error occurs
Bit 0—Keyboard Stop (KBS): Indicates the receive data stop bit. Valid only when KBF = 1.
Bit 0
KBS Description
0 0 stop bit received (Initial value)
1 1 stop bit received
17.2.2 Keyboard Control Register L (KBCRL)
Bit 76543210
KBE KCLKO KDO — RXCR3 RXCR2 RXCR1 RXCR0
Initial value01110000
Read/Write R/W R/W R/W — RRRR
KBCRL is an 8-bit readable/writable register that enables the receive counter count and controls
the keyboard buffer controller pin output.
KBCRL is initialized to H'70 by a reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bit 7—Keyboard Enable (KBE): Enables or disables loading of receive data into the keyboard
data buffer register (KBBR).
Bit 7
KBE Description
0 Loading of receive data into KBBR is disabled (Initial value)
1 Loading of receive data into KBBR is enabled