Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 544 of 1130
REJ09B0327-0400
Table 16.7 Permissible SCL Rise Time (t
Sr
) Values
Time Indication
IICX
t
cyc
Indication
I
2
C Bus
Specification
(Max.)
φ
φφ
φ =
5 MHz
φ
φφ
φ =
8 MHz
φ
φφ
φ =
10 MHz
φ
φφ
φ =
16 MHz
φ
φφ
φ =
20 MHz
07.5t
cyc
Standard
mode
1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns
High-speed
mode
300 ns 300 ns 300 ns 300 ns 300 ns 300 ns
1 17.5t
cyc
Standard
mode
1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns
High-speed
mode
300 ns 300 ns 300 ns 300 ns 300 ns 300 ns
• The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
2
C bus interface SCL and SDA output timing is prescribed by t
cyc
, as shown in
table 16.6. However, because of the rise and fall times, the I
2
C bus interface specifications may
not be satisfied at the maximum transfer rate. Table 16.8 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
t
BUFO
fails to meet the I
2
C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
2
C bus.
t
SCLLO
in high-speed mode and t
STASO
in standard mode fail to satisfy the I
2
C bus interface
specifications for worst-case calculations of t
Sr
/t
Sf
. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
timing permits this output timing for use as slave devices connected to the I
2
C bus.