Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 543 of 1130
REJ09B0327-0400
Table 16.6 I
2
C Bus Timing (SCL and SDA Output)
Item Symbol Output Timing Unit Notes
SCL output cycle time t
SCLO
28t
cyc
to 256t
cyc
ns
SCL output high pulse width t
SCLHO
0.5t
SCLO
ns
Figure 26.28
(reference)
SCL output low pulse width t
SCLLO
0.5t
SCLO
ns
SDA output bus free time t
BUFO
0.5t
SCLO
–1t
cyc
ns
Start condition output hold time t
STAHO
0.5t
SCLO
–1t
cyc
ns
Retransmission start condition output
setup time
t
STASO
1t
SCLO
ns
Stop condition output setup time t
STOSO
0.5t
SCLO
+2t
cyc
ns
Data output setup time (master) t
SDASO
1t
SCLLO
–3t
cyc
ns
Data output setup time (slave) 1t
SCLL
–(6t
cyc
or 12t
cyc
*
)
Data output hold time t
SDAHO
3t
cyc
ns
Note: * 6t
cyc
when IICX is 0, 12t
cyc
when 1.
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
cyc
, as shown in I
2
C Bus Timing in section 26,
Electrical Characteristics, and as shown in table 26.10. Note that the I
2
C bus interface AC
timing specifications will not be met with a system clock frequency of less than 5 MHz.
• The I
2
C bus interface specification for the SCL rise time t
sr
is under 1000 ns (300 ns for high-
speed mode). In master mode, the I
2
C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t
sr
(the time for SCL to go from low to V
IH
) exceeds
the time determined by the input clock of the I
2
C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.