Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 518 of 1130
REJ09B0327-0400
16.2.8 DDC Switch Register (DDCSWR)
Bit
Initial value
Read/Write
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.
7
SWE
0
R/W
6
SW
0
R/W
5
IE
0
R/W
4
IF
0
R/(W)
*
1
3
CLR3
1
W
*
2
0
CLR0
1
W
*
2
2
CLR2
1
W
*
2
1
CLR1
1
W
*
2
DDCSWR is an 8-bit readable/writable register that is used to initialize IIC and controls IIC
internal latch clearance.
DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Bit 7—DDC Mode Switch Enable (SWE): Selects the function for automatically switching IIC
channel 0 from formatless mode to the I
2
C bus format.
Bit 7
SWE Description
0 Automatic switching of IIC channel 0 from formatless mode to I
2
C bus format is
disabled (Initial value)
1 Automatic switching of IIC channel 0 from formatless mode to I
2
C bus format is
enabled
Bit 6—DDC Mode Switch (SW): Selects either formatless mode or the I
2
C bus format for IIC
channel 0.
Bit 6
SW Description
0 IIC channel 0 is used with the I
2
C bus format (Initial value)
[Clearing conditions]
1. When 0 is written by software
2. When a falling edge is detected on the SCL pin when SWE = 1
1 IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0