Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 508 of 1130
REJ09B0327-0400
Bit 2
BBSY Description
0 Bus is free (Initial value)
[Clearing condition]
When a stop condition is detected
1Bus is busy
[Setting condition]
When a start condition is detected
Bit 1—I
2
C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I
2
C bus interface has
issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave
address or general call address is detected in slave receive mode, when bus arbitration is lost in
master transmit mode, and when a stop condition is detected. IRIC is set at different times
depending on the FS bit in SAR and the WAIT bit in ICMR. See section 16.3.6, IRIC Setting
Timing and SCL Control. The conditions under which IRIC is set also differ depending on the
setting of the ACKE bit in ICCR.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
When the DTC is used, IRIC is cleared automatically and transfer can be performed continuously
without CPU intervention.