Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 500 of 1130
REJ09B0327-0400
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW FS FSX Operating Mode
000 I
2
C bus format
• SAR and SARX slave addresses recognized
1I
2
C bus format (Initial value)
• SAR slave address recognized
• SARX slave address ignored
10 I
2
C bus format
• SAR slave address ignored
• SARX slave address recognized
1 Synchronous serial format
• SAR and SARX slave addresses ignored
10
0
1
0
1
0
Formatless mode (start/stop conditions not detected)
• Acknowledge bit used
1 1 Formatless mode
*
(start/stop conditions not detected)
• No acknowledge bit
Note: * Do not set this mode when automatic switching to the I
2
C bus format is performed by
means of the DDCSWR setting.
16.2.3 Second Slave Address Register (SARX)
Bit
Initial value
Read/Write
7
SVAX6
0
R/W
6
SVAX5
0
R/W
5
SVAX4
0
R/W
4
SVAX3
0
R/W
3
SVAX2
0
R/W
0
FSX
1
R/W
2
SVAX1
0
R/W
1
SVAX0
0
R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.