Datasheet

Section 16 I
2
C Bus Interface [Option]
Rev. 4.00 Sep 27, 2006 page 492 of 1130
REJ09B0327-0400
• Wait function in slave mode (I
2
C bus format)
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
 Data transfer end (including transmission mode transition with I
2
C bus format and address
reception after loss of master arbitration)
 Address match: when any slave address matches or the general call address is received in
slave receive mode (I
2
C bus format)
 Stop condition detection
• Selection of 16 internal clocks (in master mode)
• Direct bus drive (with SCL and SDA pins)
 Two pins—P52/SCL0 and P97/SDA0—(normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
 Two pins—P86/SCL1 and P42/SDA1—(normally CMOS pins) function as NMOS-only
outputs when the bus drive function is selected.
• Automatic switching from formatless mode to I
2
C bus format (channel 0 only)
 Formatless operation (no start/stop conditions, non-addressing mode) in slave mode
 Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL)
 Automatic switching from formatless mode to I
2
C bus format on the fall of the SCL pin
16.1.2 Block Diagram
Figure 16.1 shows a block diagram of the I
2
C bus interface.
Figure 16.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins and
channel 1 I/O pins differ in structure, and have different specifications for permissible applied
voltages. For details, see section 26, Electrical Characteristics.